Pentek’s Jade Architecture SOSA Aligned LVDS XMC Module with Optical I/O Now Available

Upper Saddle River, NJ, February 01, 2019 --(PR.com)-- Pentek, Inc., today introduced the newest member of the Jade™ family of data converter XMC modules. The Model 71813 is based on the Xilinx Kintex Ultrascale FPGA and features 28 pairs of LVDS digital I/O to meet the requirements of emerging standards from The Open Group Sensor Open Systems Architecture™ (SOSA™) Consortium of which Pentek is a member. The Model 71813 is also the industry’s first such XMC to implement an optional front panel optical interface supporting four 12Gbps lanes to the FPGA.

The Model 71813 routes 28 pairs of LVDS connections from the FPGA to the XMC P16 connector for custom I/O. When mounted on a compatible single board computer, the Model 71813 provides a customizable I/O signal status and control interface. In the case of a VPX implementation, the I/O is routed to the backplane where it can handle control and command signals to the chassis being defined in the evolving SOSA initiative.

"The Jade Model 71813 directly addresses I/O needs called out in the emerging SOSA standards,” said Paul Mesibov, Pentek’s chief technical officer and SOSA standard contributor. “Pentek is working with other SOSA members and is committed to lending our experience in meeting open system architecture challenges.”

The Model 71813 can be optionally configured with a front panel MPO optical connector for supporting four lanes of 12Gbps to the FPGA. With user-installed FPGA IP, the Model 71813 can be used as an optical interface for 10GigE, 40GigE, Aurora or custom protocols.

With the Xilinx Kintex Ultrascale FPGA, LVDS digital I/O and optical I/O, the Model 71813 becomes an excellent high performance off-load co-processor to fit a wide assortment of processing needs in the most demanding of applications.

The Jade Architecture
The Pentek Jade architecture is based on the Xilinx Kintex UltraScale FPGA, which raises the digital signal processing (DSP) performance by over 50% with equally impressive reductions in cost, power dissipation and weight. Its PCI Gen.3 interface allows access to control and status registers for controlling algorithms, state machines and data flow across the LVDS SOSA I/O port and the optional front panel optical port. A 5 GB bank of DDR4 SDRAM is available for additional functions. The factory-installed DMA controller can sustain 6.4 GB/s data transfers across PCIe.

Navigator Design Suite for Streamlined IP Development
Pentek’s Navigator™ Design Suite was designed from the ground up to work with Pentek’s Jade architecture and Xilinx’s Vivado Design Suite® providing an unparalleled plug-and-play solution to the complex task of IP and control software creation and compatibility. Graphical design entry for Xilinx and Pentek AXI4-compliant IP modules using the Xilinx IP Integrator greatly speeds development tasks. The Navigator Design Suite consists of two components: Navigator FDK (FPGA Design Kit) for integrating custom IP into Pentek sourced designs and Navigator BSP (Board Support Package) for creating host applications. Users can work efficiently at the API level for software development and with an intuitive graphical interface for IP design. The Navigator BSP is available for Windows and Linux operating systems.

Pricing and Availability
For the latest pricing and availability information, please contact John Eklund by phone at (201) 818-5900, or by email at sales@pentek.com.

For access to the full release and data sheets, please visit: https://www.pentek.com/whatsnew/viewrelease.cfm?index=243