MIPI D-PHY Tx IP Core in 22nm Along with MIPI DSI-2 Tx Controller IpPCore is Available for Licensing
MIPI D-PHY Tx IP Core in 22nm along with MIPI DSI-2 Tx Controller IP Core for your High-End Camera and Display needs is available for immediate licensing.
Munich, Germany, February 23, 2022 --(PR.com)-- T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s MIPI Alliance Standard MIPI D-PHY v1.2 Tx IP Core in 22nm process node and its matching MIPI DSI-2 Tx v1.1 Controller IP Core for all types of Display and Camera applications. The D-PHY IP Core together with the DSI-2 Controller IP boasts flexibility, high speed, power efficiency and low cost.
The MIPI D-PHY Analog Tx IP Core uses PPI interface and is fully compliant to the D-PHY specification version 1.2. It supports the MIPI Camera Serial Interface (CSI-2) and Display Serial Interface (DSI protocols). The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions. The D-PHY has an internal termination resistor with auto-calibration and includes a PLL, a Clock Lane and four Data Lane for MIPI DSI data transmission. The D-PHY in 22nm process node can also be used as a 5V tolerance GPIO bank. It moderates synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s and asynchronous transfer at low power mode with a bit rate of 10 Mb/s. It also supports ultra-low power mode, high speed mode and escape mode making it highly flexible and power efficient. Data lanes support transfer of data in high-speed mode with error detection mechanism for sequence errors and contentions. Configurable skew option for each Clock and Data lanes makes it easily controllable with added feature of testability for TX, RX and PLL.
The MIPI DSI-2 Transmitter Controller IP Core is an interface between a display or any other data interface, and a host processor baseband application engine. This interface is defined by the MIPI Alliance Highly modular and configurable design. It supports 2.5 Gbps per data lane of D-PHY i.e., 10Gbps in 4 Lanes. Programmable Data Lane Configuration, Forward and reverse communication increases flexibility with support for command and video mode, burst and non-burst modes, pulse and event modes. Its Layered Structure also allows Color modes: 16, 18, 24 and 36 bpp and Display Stream Compression (DSC).
MIPI D-PHY Tx IP Core in 22nm process technology can be ported to any Fab and Node required by the customer. The IP Core can also be modified and provided as a complete solution with MIPI DSI-2 Tx Controller IP Core. The MIPI D-PHY IP and MIPI DSI-2 Tx Controller IP Core has also been used in semiconductor industry’s Multimedia SoCs, Automotive, Mobile, IoT and other Consumer Electronics…
In addition to MIPI D-PHY IPs and DSI Controller IP Cores, T2M ‘s broad silicon Interface IP Core Portfolio includes USB, MIPI, PCIe, HDMI, Display Port, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, SD/eMMCs, Serial ATA and many more Controllers with matching PHYs, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo: contact@t-2-m.com
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: https://t-2-m.com
The MIPI D-PHY Analog Tx IP Core uses PPI interface and is fully compliant to the D-PHY specification version 1.2. It supports the MIPI Camera Serial Interface (CSI-2) and Display Serial Interface (DSI protocols). The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions. The D-PHY has an internal termination resistor with auto-calibration and includes a PLL, a Clock Lane and four Data Lane for MIPI DSI data transmission. The D-PHY in 22nm process node can also be used as a 5V tolerance GPIO bank. It moderates synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s and asynchronous transfer at low power mode with a bit rate of 10 Mb/s. It also supports ultra-low power mode, high speed mode and escape mode making it highly flexible and power efficient. Data lanes support transfer of data in high-speed mode with error detection mechanism for sequence errors and contentions. Configurable skew option for each Clock and Data lanes makes it easily controllable with added feature of testability for TX, RX and PLL.
The MIPI DSI-2 Transmitter Controller IP Core is an interface between a display or any other data interface, and a host processor baseband application engine. This interface is defined by the MIPI Alliance Highly modular and configurable design. It supports 2.5 Gbps per data lane of D-PHY i.e., 10Gbps in 4 Lanes. Programmable Data Lane Configuration, Forward and reverse communication increases flexibility with support for command and video mode, burst and non-burst modes, pulse and event modes. Its Layered Structure also allows Color modes: 16, 18, 24 and 36 bpp and Display Stream Compression (DSC).
MIPI D-PHY Tx IP Core in 22nm process technology can be ported to any Fab and Node required by the customer. The IP Core can also be modified and provided as a complete solution with MIPI DSI-2 Tx Controller IP Core. The MIPI D-PHY IP and MIPI DSI-2 Tx Controller IP Core has also been used in semiconductor industry’s Multimedia SoCs, Automotive, Mobile, IoT and other Consumer Electronics…
In addition to MIPI D-PHY IPs and DSI Controller IP Cores, T2M ‘s broad silicon Interface IP Core Portfolio includes USB, MIPI, PCIe, HDMI, Display Port, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, SD/eMMCs, Serial ATA and many more Controllers with matching PHYs, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo: contact@t-2-m.com
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: https://t-2-m.com
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T2M
Mike Park
+91 9923060006
www.t-2-m.com
Mike Park
+91 9923060006
www.t-2-m.com
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